VLSI PROJECTS

VLSI 001    IMAGE STEGANOGRAPHY           
VLSI 002    MINI UART          
VLSI 003    SINE WAVE GENERATOR         
VLSI 004    CONSTRUCTION OF PIANO           
VLSI 005    AN AREA - EFFICIENT UNIVERSAL CRYPTOGRAPHY PROCESSOR FOR SMART   CARDS      
VLSI 006    MULTI-FUNCTION CALCULATOR USING AN ALU       
VLSI 007    DESIGN OF BOOTH MULTIPLIER        
VLSI 008    PSEUDO RANDOM SEQUENCE GENERATOR USING LFSR      
VLSI 009    CONSTRUCTION OF SYNCHRONOUS FIFO      
VLSI 010    A VLSI ARCHITECTURE FOR RIJNDAEL, THE ADVANCED ENCRYPTION            STANDARD      
VLSI 011    VITERBI HDL CODE GENERATOR (VHCG)      
VLSI 012    DESIGN OF FIBONACCI GENERATOR         
VLSI 013    DESIGN OF FLOATING POINT PROCESSOR          
VLSI 014    ANALOG-TO-DIGITAL CONVERTER ONVERTER MODEL      
VLSI 015    GENERIC LARGE-CAPACITY RAM MODE           
VLSI 016    BAUD RATE GENERATOR      
VLSI 017    BIST CIRCUITS      
VLSI 018    SIMPLE BUS INTERFACE       
VLSI 019    8-BIT MICROPROCESSOR IN VHDL      
VLSI 020    DESIGN OF GREATEST COMMON DIVISER          
VLSI 021    HEAP SORT PARALLEL      
VLSI 022    DESIGN OF LCM          
VLSI 023    MINIMUM NUMBER OF ARRAY         
VLSI 024    CONSTRUCTION OF PARITY & CRC32 GENERATOR AND DETECTOR      
VLSI 025    CONSTRUCTION OF SHIFT REGISTER WITH CONTROL INPUTS      
VLSI 026    DESIGN OF SORTER      
VLSI 027    SPECTRUM SPREADER      
VLSI 028    DESIGN OF SQUARE NO GENERATOR      
VLSI 029    SYNCHRONIZER SCALAR      
VLSI 030    LOW POWER FIR FILTER      
VLSI 031    TRAFFIC LIGHT CONTROLLER      
VLSI 032    DESIGN OF PROGRAMMABLE DMA CONTROLLER      
VLSI 033    SEQUENCE GENERATOR      
VLSI 034    BINARY MULTIPLIER USING  ADD & SHIFT METHOD      
VLSI 035     HIGHWAY SPEED MEASURING SYSTEM        
VLSI 036    RS -232 SERIAL TRANSMISSION      
VLSI 037    HARDWARE IMAGE COMPRESSION (HICo-wiF)      
VLSI 038    DESIGN OF PROGRAMMABLE INTERERRUPT CONTROLLER      
VLSI 039    DELTA SIGMA CONVERTER      
VLSI 040    DATA ENCRYPTION STANDARD      
VLSI 041      DCT - DISCRETE COSINE TRANSFORMER      
VLSI 042    AREA OPTIMIZED ARCHITECTURE AND VISI IMPLEMENTATION OF RC5 ENCRYPTION ALGORITHM

Posted in: JNTU FINAL YEAR MAIN PROJECTS FOR BTECH